1. Field of the Invention
The present invention relates to a semiconductor package and fabrication method thereof, and in particular, to a lead frame structure and semiconductor package using the same and fabrication method thereof for a semiconductor package.
2. Background of the Related Art
In general, a semiconductor packaging protects a semiconductor chip. With advanced process techniques, semiconductor chips have gradually decreased in size. Accordingly, faster computer systems require a highly integrated semiconductor. To provide optimal operating conditions of such a system, an internal noise of the system should be decreased or minimized.
With regard to such internal noise, an electro-magnetic cross-talk noise that is known to be disadvantageous only in a board level of the system also critically effects at a semiconductor chip level. Namely, an integrated semiconductor package serves to increase a clock frequency. As a wavelength of a signal becomes closer to a wirelength, an interconnection line comes to operate like an antenna that increases a radiation noise. Also, there is an increased coupling such as a capacitive, an inductive, and a resistive coupling between interconnection lines because a wire interval becomes relatively narrowed with high integration. Thus, an electromagnetic cross-talk noise is increased and accordingly the system capability is deteriorated.
Another factor that lowers the system function is attributed to a simultaneous switching noise that is referred to as delta-I noise or di/dt noise (hereinafter "delta-I noise"). The delta-I noise results from a power line in the internal system or from a ground line. An electromotive force (E) that occurs in an inductor is obtained by an inductance (L) times a current variation amount per hour (di/dt) or by E=L(di/dt). A current outputted from a power source suffers a voltage drop due to a reverse electromotive force induced while passing through the inductor of the power line. Thus, a supply voltage provided to a required circuit becomes much lower than the initial voltage, which frequently causes an erroneous operation. Further, as chip integration increases, and more input/output ports are required, an entire capacitive load also becomes greater. For faster circuit operation, the capacitive load should be charged or discharged in a faster manner so that an average current and the current variation amount per hour (di/dt) can increase. However, the increased average current and the current variation amount per hour (di/dt) causes further delta-I noise.
FIG. 1 illustrates a plan view of a related art lead frame structure for a Quad Flat Package (QFP). The frame structure includes a paddle 11 for attaching a chip thereon, a tie bar 12 extended outwardly from each corner of the paddle 11 and supporting the paddle 11 and a plurality of leads 13 aligned proportionally around the paddle 11. The leads 13 are composed of signal leads, power leads and ground leads, depending on their functions.
Although the above-mentioned disadvantages have to do with interconnection lines within a system circuit, a lead frame equipped inside a semiconductor package may be an additional, more serious problem. Respective leads of the lead frame are longer than the connection lines, and the inductance and capacitance of the leads become larger than those of the interconnection lines. Therefore, a packaging structure is needed that may decrease or minimize such problems as electromagnetic cross-talk noise and delta-I noise.